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| Click Here & Upgrade PDF Complete Documents Expanded Features Unlimited Pages SPICE Device Model SI4963BDY Vishay Siliconix Dual P-Channel 2.5-V (G-S) MOSFET CHARACTERISTICS * P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72770 20-May-04 www.vishay.com 1 Click Here & Upgrade PDF Complete SPICE Device Model SI4963BDY Vishay Siliconix Documents Expanded Features Unlimited Pages SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current b Symbol Test Conditions Simulated Data Measured Data Unit VGS(th) ID(on) b VDS = VGS, ID = -250 A VDS = -5 V, VGS = -4.5 V VGS = -4.5 V, ID = -6.5 A VGS = -2.5 V, ID = -2 A VDS = -10 V, ID = -6.5 A IS = -1.7 A, VGS = 0 V 1.1 92 0.025 0.041 16 -0.80 0.025 0.040 18 -0.75 V A S V Drain-Source On-State Resistance Forward Transconductance Diode Forward Voltage b b rDS(on) gfs VSD Dynamic a Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf VDD = -10 V, RL = 10 ID -1 A, VGEN = -4.5 V, RG = 6 VDS = -10 V, VGS = -4.5 V, ID = - 6.5 A 12 2.6 4.6 30 22 65 20 14 2.6 4.6 25 30 70 50 ns nC Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width 300 s, duty cycle 2%. www.vishay.com 2 Document Number: 72770 20-May-04 Click Here & Upgrade PDF Complete Documents Expanded Features Unlimited Pages SPICE Device Model SI4963BDY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 72770 20-May-04 www.vishay.com 3 |
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